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HT16270
RAM Mapping 64 16 LCD Controller for I/O mC
Features
* * * * * * * * *
Operating voltage: 2.7V~5.2V External Crystal 32.768kHz oscillator 1/5 bias, 1/16 duty, frame frequency is 64Hz Max. 6416 patterns, 16 commons, 64 segments Built-in internal resistor type bias generator 3-wire serial interface 8 kinds of time base/WDT selection Time base or WDT overflow output Built-in LCD display RAM
* * * * * * *
R/W address auto increment Two selectable buzzer frequencies (2kHz/4kHz) Power down command reduces power consumption Software configuration feature Data mode and Command mode instructions Three data accessing modes VLCD pin to adjust LCD operating voltage
General Description
HT16270 is a peripheral device specially designed for I/O type mC used to expand the display capability. The max. display segment of the device are 1024 patterns (6416). It also supports serial interface, buzzer sound, watchdog timer or time base timer functions. The H T 1 6 2 7 0 i s a m em or y m a p p i n g a n d multi-function LCD controller. The software configuration feature of the HT16270 make it suitable for multiple LCD applications including LCD modules and display subsystems. Only three lines are required for the interface between the host controller and the HT16270. The HT162X series have many kinds of products that match various applications.
Selection Table
HT162X COM SEG Built-in Osc. Crystal Osc. O HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270 4 32 4 32 O O 8 32 O O 8 32 8 48 O O 8 64 O O 16 48 O O 16 64 O O 16 64
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HT16270
Block Diagram
OSCO OSCI CS RD WR DATA VDD VSS BZ BZ T o n e F re q u e n c y G e n e ra to r W a tc h d o g T im e r and T im e B a s e G e n e r a to r C o n tro l and T im in g C ir c u it COM0 L C D D r iv e r / B ia s C ir c u it CO M 15 SEG0 SEG 63 VLCD IR Q D is p la y R A M
Pin Assignment
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG CS RD WR DATA VSS OSCI OSCO VDD VLC D IR Q BZ BZ T1 T2 T3 T4 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 C O M 10 C O M 11 C O M 12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50 100 99 98 97 96 9594 93 92 91 90 89 88 87 86 85 84 83 82 81 63 13 62 14 61 15 60 0 59 1 58 2 57 3 56 4 55 5 54 6 53 7 52 8 51 9 50 10 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG SEG NC SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG NC NC SEG SEG 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
HT16270 100 Q FP
18 17
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM 11 12 13 14
2
15
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HT16270
Pad Assignment
SEG 59 SEG 60 SEG 63 SEG 61 SEG 62 SEG 57 SEG 58 SEG 55 SEG 56 SEG 53 SEG 54 SEG 51 SEG 52 SEG 49 SEG 50 SEG 47 SEG 48 SEG 45 SEG 46 SEG 43 SEG 44 SEG 42 WR
96 1 2 3 4 5 6 7 8
CS
94
RD
95
93
92
91
90
89
88
87
86
85
84 83
82
81
80
79
78
77
76
75
74
73
72 71 70 69 68 67 66 65 64 63
DATA VS OS OSC VD VLC S CI O D D
SEG 41 SEG 40 SEG 39 SEG 38 SEG 37 SEG 36 SEG 35 SEG 34 SEG 33 SEG 32 SEG 31 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 SEG 22 SEG 21 SEG 20 SEG 19
IR Q BZ
BZ T1 T2 T3 T4 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
62 61
(0 , 0 )
60 59 58 57 56 55 54 53 52 51 50 49 48
SEG8 SEG7
SEG 17
SEG0 CO M 15
SEG 18
CO M 14 CO M 13
SEG4 SEG3
CO M 12 CO M 11
SEG6 SEG5
SEG 16 SEG 15
SEG 10 SEG9
SEG2 SEG1
SEG 12 SEG 11
* The IC substrate should be connected to VDD in the PCB layout artwork.
CO M 10
SEG 14 SEG 13
Chip size: 245 237 (mil)
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HT16270
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 X -116.57 -116.68 -116.72 -116.72 -116.72 -115.93 -116.72 -116.72 -116.72 -115.94 -115.94 -115.94 -115.90 -115.97 -115.93 -115.93 -115.93 -115.93 -115.97 -115.93 -115.93 -115.94 -115.94 -108.08 -96.03 -89.43 -77.43 -70.82 -58.83 -52.17 -40.22 -33.58 -21.58 -14.98 -2.97 3.67 15.63 22.27 34.28 40.88 52.88 59.47 71.47 78.13 90.07 96.72 108.72 116.19 Y 99.90 90.80 84.15 77.50 70.90 64.25 54.75 41.45 21.85 11.39 -0.60 -7.18 -19.21 -25.85 -37.85 -44.45 -56.45 -63.05 -75.05 -81.70 -93.65 -100.30 -112.37 -112.07 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.00 -112.05 -112.00 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.00 -112.00 -112.05 -112.05 -112.00 -111.82 Pad No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
4
Unit: mil X 116.15 116.15 116.19 116.19 116.15 116.19 116.19 116.19 116.19 116.19 116.19 116.24 116.24 116.19 116.24 116.19 116.19 116.15 116.15 116.19 116.15 116.19 116.11 112.20 100.04 93.42 81.43 74.80 62.77 56.23 44.20 37.57 25.63 18.95 6.97 0.38 -11.65 -18.23 -30.22 -36.89 -48.92 -55.51 -67.45 -74.12 -86.15 -92.72 -104.72 -114.22 Y -99.79 -93.16 -81.18 -74.54 -62.58 -55.93 -43.94 -37.40 -25.37 -18.70 -6.72 -0.09 11.90 18.49 30.51 37.10 49.09 55.76 67.75 74.38 86.36 93.03 104.85 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.20 112.24 112.24 112.24 112.24 112.29 112.24 112.24 112.25 112.25 112.25
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HT16270
Pad Description
Pad No. 1 2 3 4 5 6 7 8, 9 10~13 14~29 30~93 Pad Name DATA VSS OSCI OSCO VDD VLCD IRQ BZ, BZ T1~T4 COM0~COM15 SEG0~SEG63 I/O 3/4 I O 3/4 I O O I O O Description Negative power supply, ground Crystal oscillator input pin Crystal oscillato output pin Positive power supply LCD operating voltage input pad. Time base or watchdog timer overflow flag, NMOS open drain output 2kHz or 4kHz tone frequency output pair (Tristate output buffer) Not connected LCD common outputs LCD segment outputs Chip selection input with pull-high resistor. When the CS is logic high, the data and command read from or write to the HT16270 are disabled. The serial interface circuit is also reset. But if the CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT16270 are all enabled. READ clock input with pull-high resistor. Data in the RAM of the HT16270 are clocked out on the rising edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next falling edge to latch the clocked out data. WRITE clock input with pull-high resistor. Data on the DATA line are latched into the HT16270 on the rising edge of the WR signal. I/O Serial data input/output with pull-high resistor
94
CS
I
95
RD
I
96
WR
I
Absolute Maximum Ratings
Supply Voltage .............................-0.3V to 5.5V Input Voltage .................VSS-0.3V to VDD+0.3V Storage Temperature.................-50C to 125C Operating Temperature ..............-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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D.C. Characteristics
Symbol VDD IDD1 IDD2 ISTB VIL VIH IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 IOL4 IOH4 RPH Parameter Operating Voltage Operating Current Operating Current Standby Current Input Low Voltage Input High Voltage BZ, BZ, IRQ BZ, BZ DATA DATA LCD Common Sink Current LCD Common Source Current LCD Segment Sink Current LCD Segment Source Current Pull-high Resistor Test Conditions VDD 3/4 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V Conditions 3/4 No load/LCD ON Crystal oscillator No load/LCD OFF Crystal oscillator No load Power down mode DATA, WR, CS, RD DATA, WR, CS, RD VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V DATA, WR, CS, RD Ta=25C Min. Typ. Max. Unit 2.7 3/4 3/4 3/4 3/4 3/4 3/4 0 0 2.4 4.0 0.9 1.7 -0.9 -1.7 0.9 1.7 -0.9 -1.7 80 180 -40 -90 50 120 -30 -70 100 50 3/4 30 50 5 10 2 4 3/4 3/4 3/4 3/4 1.8 3 -1.8 -3 1.8 3 -1.8 -3 160 360 -80 -180 100 240 -60 -140 200 100 5.2 75 125 25 45 14 28 0.6 1.0 3 5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 300 150 V mA mA mA mA mA mA V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA kW kW
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HT16270
A.C. Characteristics
Symbol fSYS fLCD tCOM fCLK1 fCLK2 tCS Parameter System Clock LCD Frame Frequency LCD Common Period Serial Data Clock (WR Pin) Serial Data Clock (RD Pin) Serial Interface Reset Pulse Width (Figure 3) Test Conditions VDD 3V 5V 3V 5V 3/4 3V 5V 3V 5V 3/4 3V 5V 3V 5V Conditions Crystal oscillator Crystal oscillator n: Number of COM Duty cycle 50% Duty cycle 50% CS Write mode Read mode Write mode Read mode 3/4 3/4 3/4 3/4 3/4 Min. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3.34 6.67 1.67 3.34 3/4 3/4 3/4 3/4 3/4 Typ. 32 32 64 64 n/fLCD 3/4 3/4 3/4 3/4 250 3/4 3/4 3/4 3/4 120 120 120 100 100 Ta=25C Max. Unit 3/4 3/4 3/4 3/4 3/4 150 300 75 150 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 kHz kHz Hz Hz sec kHz kHz kHz kHz ns ms ms ns ns ns ns ns
tCLK
WR, RD Input Pulse Width (Figure 1)
tr, tf tsu th tsu1 th1
Rise/Fall Time Serial Data Clock Width (Figure 1)
Setup Time for DATA to WR, RD 3V Clock Width (Figure 2) 5V Hold Time for DATA to WR, RD 3V Clock Width (Figure 2) 5V 3V Setup Time for CS to WR, RD Clock Width (Figure 3) 5V 3V Hold Time for CS to WR, RD Clock Width (Figure 3) 5V
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HT16270
V A L ID D A T A DB V th
u DD
tf W R,RD C lo c k 90% 50% 10%
tr
50% ts
-V tC
LK
DD
GND V
DD
tC
LK
GND
W R,RD C lo c k
50%
-G N D
Figure 1
tC
S
Figure 2
CS
50% ts
u1
-V
DD
th
1
GND -V
DD
W R,RD C lo c k
50% F IR S T C lo c k
LAST C lo c k
GND
Figure 3
Functional Description
Display memory - RAM structure The static display RAM is organized into 2564 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessedbytheREAD,WRITEand READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns.
CO M 15 SEG0 SEG1 SEG2 SEG3 7 11 15 8 12 A d d r e s s 8 B its (A 7 , A 6 , ...., A 0 ) CO M 14 CO M 13 CO M 12 3 4
Time base and watchdog timer - WDT The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will remain at logic low level until the CLR WDT or the IRQ DIS command is issued.
COM3 COM2 COM1 COM0 0
SEG 63 D3 D2 D1 D0
255 Addr D a ta D3 D2 D1 D0
252 Addr D a ta
D a ta 4 B its (D 3 , D 2 , D 1 , D 0 )
RAM mapping
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HT16270
T im e B a s e C lo c k S o u r c e /2 5 6 V C L R T im e r
DD
T IM E R
E N /D IS
IR Q
W D T E N /D IS D CK R Q IR Q E N /D IS
W DT /4
CLR
W DT
Timer and WDT configurations If an external clock is selected as the source of system frequency, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed. Buzzer tone output A simple tone generator is implemented in the HT16270. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. Command format The HT16270 can be configured by the software setting. There are two mode commands to configure the HT16270 resource and to transfer the LCD display data. Name TONE OFF TONE 4K TONE 2K Command Code 0000-1000-X 010X-XXXX-X 0110-XXXX-X Turn-off tone output Turn-on tone output, tone frequency is 4kHz Turn-on tone output, tone frequency is 2kHz The following are the data mode ID and the command mode ID: Operation READ WRITE READ-MODIFY-WRITE COMMAND Mode Data Data Data ID 110 101 101
Command 1 0 0
If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to 1 and the previous operation mode will be reset also. The CS pin returns to 0, a new operation mode ID should be issued first. Function
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HT16270
Timing Diagrams
READ mode (command code : 1 1 0)
CS
WR
RD
DATA
1 1
0
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3 1
1
0
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
M e m o ry A d d re s s 1 (M A 1 )
D a ta (M A 1 )
M e m o ry A d d re s s 2 (M A 2 )
D a ta (M A 2 )
READ mode (successive address reading)
CS
WR
RD
DATA
1 1
0
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
M e m o ry A d d re s s (M A )
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 2 )
D a ta (M A + 3 )
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HT16270
WRITE mode (command code : 1 0 1)
CS
WR
DATA
1 0
1
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3 1
0
1
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
M e m o ry A d d re s s 1 (M A 1 )
D a ta (M A 1 )
M e m o ry A d d re s s 2 (M A 2 )
D a ta (M A 2 )
WRITE mode (successive address writing)
CS
WR
DATA
1 0
1
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
M e m o ry A d d re s s (M A )
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 2 )
D a ta (M A + 3 )
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HT16270
READ-MODIFY-WRITE mode (command code : 1 0 1)
CS
WR
RD
DATA
1 0
1
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3 1
0
1
A7
A6
A1
A0
D0
D1
D2
D3
M e m o ry A d d re s s 1 (M A 1 )
D a ta (M A 1 )
D a ta (M A 1 )
M e m o ry A d d re s s 2 (M A 2 )
D a ta (M A 2 )
READ-MODIFY-WRITE mode (successive address accessing)
CS
WR
RD
DATA
1 0
1
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
M e m o ry A d d re s s (M A )
D a ta (M A )
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 1 )
D a ta (M A + 2 )
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HT16270
Command mode (command code : 1 0 0)
CS
WR
DATA
1 0
0
C8
C7
C6
C5
C4
C3
C2
C1
C0 C o m m a n d ...
C8
C7
C6
C5
C4
C3
C2
C1
C0 Com m and or D a ta M o d e
Com m and 1
Com m and i
Mode (data and command mode)
CS
WR
DATA
Com m and or D a ta M o d e
A d d re s s a n d D a ta
Com m and or D a ta M o d e
A d d re s s a n d D a ta
Com m and or D a ta M o d e
A d d re s s a n d D a ta
RD
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HT16270
Application Circuits
CS * RD WR VLCD VDD *V R
mC
*R
DATA
H T16270
BZ P ie z o
BZ
IR Q
OSCI CO M 0~CO M 15 SEG 0~SEG 63 OSCO
C r y s ta l 3 2 7 6 8 H z o s c illa to r
1 /5 B ia s , 1 /1 6 D u ty
LCD
*Note:
Panel
The connection of IRQ and RD pin can be selected depending on the requirement of the mC. The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW20%. Adjust R (external pull-high resistance) to fit users time base clock.
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HT16270
Command Summary
Name READ WRITE READMODIFYWRITE SYS DIS SYS EN LCD OFF LCD ON WDT DIS WDT EN ID Command Code D/C D D D C C C C C C C C C C C C C C C C C C C C Function Read data from the RAM Write data to the RAM Read and Write data to the RAM Turn off both system oscillator and LCD bias generator Turn on system oscillator Turn off LCD display Turn on LCD display Disable time base output Enable time base output Enable WDT time-out flag output Turn off tone outputs Clear the contents of the time base generator Clear the contents of the WDT stage Tone frequency output: 4kHz Tone frequency output: 2kHz Disable IRQ output Enable IRQ output Time base clock output: 1Hz The WDT time-out flag after: 4s Time base clock output: 2Hz The WDT time-out flag after: 2s Time base clock output: 4Hz The WDT time-out flag after: 1s Time base clock output: 8Hz The WDT time-out flag after: 1/2 s Time base clock output: 16Hz The WDT time-out flag after: 1/4 s Yes Yes Yes Disable WDT time-out flag output Yes Yes Yes Def. 1 1 0 A7A6A5A4A3A2A1A0D0D1D2D3 1 0 1 A7A6A5A4A3A2A1A0 D0D1D2D3 1 0 1 A7A6A5A4A3A2A1A0 D0D1D2D3 1 0 0 0000-0000-X 1 0 0 0000-0001-X 1 0 0 0000-0010-X 1 0 0 0000-0011-X 1 0 0 0000-0101-X 1 0 0 0000-0111-X
TIMER DIS 1 0 0 0000-0100-X TIMER EN 1 0 0 0000-0110-X TONE OFF 1 0 0 0000-1000-X CLR TIMER 1 0 0 0000-1101-X CLR WDT TONE 4K TONE 2K IRQ DIS IRQ EN F1 F2 F4 F8 F16 1 0 0 0000-1111-X 1 0 0 010X-XXXX-X 1 0 0 0110-XXXX-X 1 0 0 100X-0XXX-X 1 0 0 100X-1XXX-X 1 0 0 101X-0000-X 1 0 0 101X-0001-X 1 0 0 101X-0010-X 1 0 0 101X-0011-X 1 0 0 101X-0100-X
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HT16270
Name F32 F64 F128 TEST NORMAL ID Command Code D/C C C C C C Function Time base clock output: 32Hz The WDT time-out flag after: 1/8 s Time base clock output: 64Hz The WDT time-out flag after: 1/16 s Time base clock output: 128Hz Yes The WDT time-out flag after: 1/32 s Test mode, user dont use. Normal mode Yes Def.
1 0 0 101X-0101-X 1 0 0 101X-0110-X 1 0 0 101X-0111-X 1 0 0 1110-0000-X 1 0 0 1110-0011-X
Note: X : Dont care A7~A0 : RAM address D3~D0 : RAM data D/C : Data/Command mode Def. : Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from a 32.768kHz crystal oscillator or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT16270 after power on reset, for power on reset may fail, which in turn leads to malfunctioning of the HT16270.
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HT16270
Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright O 2000 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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April 21, 2000

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